Entity
entity my_entity is
  port(
    i_in  : in  std_logic;
    o_out : out std_logic
  );
end my_entity;
Architecture
architecture my_arch of my_entity is
-- Déclarations de signaux, types, composants, etc.
begin
-- Assignations, process, etc.
end my_arch;
Opérateurs binaires
  • NOT
s <= not a;
  • AND
s <= a and b;
  • OR
s <= a or b;
  • NAND
s <= a nand b;
  • NOR
s <= a nor b;
  • XOR
s <= a xor b;
Multiplexeur
  • Instruction concurrente d’assignation conditionnelle
s <= a1 when (sel = "00") else
     a2 when (sel = "01") else
     a3 when (sel = "10") else
     a4;
  • En utilisant un process
p_mux : process(a1,a2,a3,a4,sel)
begin
 case sel is
   when "00"   => s <= a1 ;
   when "01"   => s <= a2 ;
   when "10"   => s <= a3 ;
   when others => s <= a4 ;
 end case;
end process p_mux;
Bascule (Flip-Flop)

signal q : std_logic;
  • Reset asynchrone
p_asynchronous_reset: process(clk, rst)
begin
  if rst = '1' then
     q <= '0';
  elsif rising_edge(clk) then
     q <= d;
  end if;
end process p_asynchronous_reset;
  • Reset synchrone
p_synchronous_reset: process(clk)
begin
  if rising_edge(clk) then
     if rst = '1' then
        q <= '0';
     else
        q <= d;
     end if;
  end if;
end process p_synchronous_reset;
Registre
signal q : std_logic_vector(n downto 0);
  • Reset asynchrone
p_asynchronous_reset: process(clk, rst)
begin
  if rst = '1' then
     q <= (others => '0');
  elsif rising_edge(clk) then
     q <= d;
  end if;
end process p_asynchronous_reset;
  • Reset synchrone
p_synchronous_reset: process(clk)
begin
  if rising_edge(clk) then
     if rst = '1' then
        q <= (others => '0');
     else
        q <= d;
     end if;
  end if;
end process p_synchronous_reset;
Additionneur
signal s_value : std_logic_vector(3 downto 0);

process(clk, rst) is begin
  if rst = '1' then
     q <= (others => '0');
  elsif rising_edge(clk) then
    if en = '1' then
      if init = '1' then
        s_value <= init_value;
      else
        s_value <= s_value + 1;
      end if;
    else
      s_value <= s_value;
    end if;
  end if;
end process;