Verilog

Module

module my_entity (
  input  wire i_in,
  output wire o_out
);
  // ports et logique interne ici
endmodule

Opérateurs binaires

assign s = ~a;

assign s = a & b;

assign s = a | b;

NAND

assign s = ~(a & b); // NAND

assign s = ~(a | b); // NOR

assign s = a ^ b;

Multiplexeur

Avec l’opérateur ternaire (assign concurrent)

assign s = (sel == 2'b00) ? a1 :
           (sel == 2'b01) ? a2 :
           (sel == 2'b10) ? a3 : a4;

En utilisant always / case

reg [WIDTH-1:0] s;
always @(*) begin
  case (sel)
    2'b00: s = a1;
    2'b01: s = a2;
    2'b10: s = a3;
    default: s = a4;
  endcase
end

Bascule (Flip-Flop)

// signal q : std_logic -> reg en Verilog
reg q;

Reset asynchrone

always @(posedge clk or posedge rst) begin
  if (rst)
    q <= 1'b0;
  else
    q <= d;
end

Reset synchrone

always @(posedge clk) begin
  if (rst)
    q <= 1'b0;
  else
    q <= d;
end

Registre

// signal q : std_logic_vector(n downto 0) -> reg [n:0] q;
reg [N:0] q;

Reset asynchrone

always @(posedge clk or posedge rst) begin
  if (rst)
    q <= { (N+1){1'b0} };
  else
    q <= d;
end

Reset synchrone

always @(posedge clk) begin
  if (rst)
    q <= { (N+1){1'b0} };
  else
    q <= d;
end

Additionneur

reg [3:0] s_value;

always @(posedge clk or posedge rst) begin
  if (rst) begin
    s_value <= 4'b0000;
  end else begin
    if (en) begin
      if (init)
        s_value <= init_value; // init_value doit avoir la même largeur
      else
        s_value <= s_value + 1;
    end
    // sinon on garde la valeur courante (pas d'affectation nécessaire)
  end
end